An open source digital design conference

We're pleased to announce that ORCONF 2016 will be held between October 7 to October 9 at the University of Bologna, in Bologna, Italy.

ORCONF is an open source digital design and embedded systems conference, covering areas of electronics from the transistor level up to Linux user space and beyond. Expect presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name a few.

Begun as the annual OpenRISC developers and users conference, it has become a broad open source digital design-oriented event and is supported by FOSSi - the Free and Open Source Silicon Foundation.

The conference is free to attend, and we invite anyone with an interest in the field to participate by presenting or just joining us for the event.

Register

We have now disabled the registration form for the event. Please email us at orconf@fossi-foundation.org to find out if we have space.

If you would like to present this year, we still might be able to fit in a short talk or two, so please fill out this form.

Venue

The conference will take place at the University of Bologna School of Engineering and Architecture in Bologna, Italy.

The address of the venue is Viale del Risorgimento, 2, 40136 Bologna.

The room is Aula Magna on the second floor of the building.

Previous editions:latest 2015 2014 2013 2012

Travel and accommodation

Bologna is easily accessible via air, rail and road. Wikivoyage has a reasonable guide on transport options.

It is a city of a few-hundred thousand people, and there should be plenty of accommodation options available through the usual booking sites.

Two hotels which have been booked by conference organisers and attendees are Hotel Renzo and Hotel Centrale.

Schedule

Conference start and end

The conference will begin at 1PM on Friday October 7th and conclude at 3PM on Sunday October 9th.

Running order

The running order can be found here.

Conference dinner

As is tradition we will arrange a dinner on Saturday evening which can accommodate all conference attendees and any family or friends who might be in town with them; everyone is invited to attend.

The venue this year is Altro. We are still finalizing arrangements, and will send out a questionnaire for people to fill in for their food order for the evening in advance.

2016 presentations and bios

Open-source Hardware: Opportunities and Challenges

Innovation in hardware is slowing due to rising costs of chip design and diminishing benefits from Moore’s law and Dennard scaling. Software innovation, on the other hand, is flourishing, helped in good measure by a thriving open-source ecosystem. We believe that open source can similarly help hardware innovation, but has not yet due to several reasons. We identify these reasons and how the industry, academia, and the hardware community at large can come together to address them. IEEE Computer paper.

Presenter: Gagan Gupta

Gagan Gupta leads research efforts related to chips for DNA storage and post-Moore’s Law microprocessors at Microsoft Research. Gupta has held leadership positions across engineering and research in the industry for over two decades. He has designed computer chips that have shipped in millions of path-breaking systems such as Silicon Graphics workstations, Sony Playstations and Huawei routers. He has authored multiple award-winning publications and his work has been covered by New York Times, EE Times, Microprocessor Report, Engineering & Technology, Business Wire, Electronic Design, and New Electronics.

lowRISC: an update on our efforts to produce an open-source SoC

The lowRISC project was announced to the world two years ago at ORConf 2014. Since then, we have been working tirelessly towards our goal of producing a completely open-source SoC. Among other things, we have been working on novel security features (tagged memory), and post-tapeout flexibility (minion cores).

This talk will describe our current status and recent developments, give an overview of our roadmap going forwards, and discuss how you can help us achieve our goal of becoming the 'Linux of the hardware world'.

Presenter: Alex Bradbury

Alex Bradbury (@asbradbury) is a co-founder of the lowRISC project and a researcher at the University of Cambridge Computer Laboratory where he has spent many years researching novel compilation techniques for many-core architectures. He is currently working on an upstreamed RISC-V port of LLVM. Prior to lowRISC, he was heavily involved in the Raspberry Pi project.

BOOM: A Superscalar Out-of-order RISC-V Processor

BOOM is an open source superscalar out-of-order RISC-V core that is roughly equivalent in performance and area to a Cortex A9 or A15 processor. BOOM supports the full RV64G RISC-V ISA (including the Privileged and External Debug specifications), provides good single-thread performance competitive with contemporary processors, is written in a free and open hardware construction language (Chisel), targets both ASIC and FPGA flows, and is accompanied by an open source design specification.

In this talk we will discuss some of the latest updates to BOOM and the larger Rocket-chip SoC ecosystem that BOOM integrates with. We will also discuss the new Chisel3 hardware construction language and its new FIRRTL-based (a Flexible IR for RTL) flow, which helps open up the world of writing compiler passes to hardware designers for fun and profit.

Presenter: Chris Celio

Chris Celio is a PhD candidate at UC Berkeley advised by Krste Asanovic and David Patterson. He received his B.S. and M.Eng. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. For his PhD thesis, he has been designing and implementing the open source processor BOOM, with the goal to provide a high-quality and high-performance core for the community to use for research, education, and industry.

Formal Verification with Yosys-SMTBMC

Yosys is a free and open source Verilog synthesis tool and more. It gained prominence last year because of its role as synthesis tool in the Project IceStorm FOSS Verilog-to-bitstream flow for iCE40 FPGAs. This presentation however dives into the Yosys-SMTBMC formal verification flow that can be used for verifying formal properties using bounded model checks and/or temporal induction.

The presentation covers practical examples of how to set up and use the flow, but also touches on in-depth topics such as the scheme used by Yosys-SMTBMC to encode a temporal circuit problem using the SMT-LIB v2.5 language (utilizing uninterpreted functions and user-declared sorts).

Presenter: Clifford Wolf

Clifford Wolf is the author of Yosys, Project IceStorm, and a few other FOSS projects. His interests and hobbies are FOSS EDA, formal methods, data science and machine learning, GPGPUs, the game of Go, and riding an electric unicycle.

PULP: an open source Parallel Ultra-Low-Power computing platform

PULP is a RISC-V based multi-core platform that leverages near-threshold computing and multi-core parallelism to provide high performance and energy efficiency while maintaining the flexibility and programmability typical of instruction processors to target requirements of a number of high-growth near-sensor processing Internet of Things (IoT) applications.

PULP supports OpenMP, OpenCL and OpenVX parallel programming models on top of GCC and LLVM toolchains. A virtual platform allows early application development and debug, while a RTL cycle accurate Xilinx Zynq-based FPGA emulation platform with support for debug and instruction tracing is available for development and benchmarking of real-life applications. An expansion board for Zynq integrating several sensors, including low power imagers, MEMS microphones, and accelerometers, has been developed to emulate real-life application environments.

Multiple silicon implementations of PULP have been taped out in several technology nodes and achieve hundreds of GOPS/W on video, audio, inertial sensor data processing and classification, within power envelopes of a few milliwatts. PULP hardware and software are open-source with the goal of supporting and boosting an innovation ecosystem focusing on ULP computing for the IoT.

The purpose of this talk is to present recent evolutions of PULP to the ORCONF community, with the goal of sharing the hardware/software PULP infrastructure, as well as silicon prototypes and application boards.

Presenter: Davide Rossi

Davide Rossi is an assistant professor at the department of Electronic and Information Engineering “Guglielmo Marconi” at the University of Bologna. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures, design implementation strategies, and runtime support to address performance, energy efficiency, and reliability issues of both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain.

The ZipCPU: A resource efficient 32-bit SoftCore

Now that FPGAs have become powerful and ubiquitous enough, there exist many soft core CPUs that can be placed within FPGAs to accomplish sequential tasks. Among these are the proprietary CPU's Microblaze and Nios, as well as the open CPUs of OpenRISC and RISC-V. These CPUs, however, tend to be built with the generic purpose of turning an FPGA into a high quality CPU, rather than complementing the FPGA's strength by augmenting some specialized FPGA algorithm with some amount of sequential logic. This focus can be seen in both the area these CPUs take up, as well as the complexity of their interface to the rest of the FPGA's logic and memory.

In contrast, the ZipCPU has been designed from the ground up with a focus on simplified logic and on-chip interaction. It does this by using a stripped down instruction set, as well as a stripped down interrupt and wishbone bus model. This allows the ZipCPU to fit within the small spaces left over within larger designs, as exemplified by the fact that it can easily fit within a Spartan-LX4, using only 1215 LUTs.

Presenter: Dan Gisselquist

Dr. Gisselquist is the lead engineer and owner of Gisselquist Technology, LLC, a services based company focused on providing superior Computer Engineering and Signal Processing services to our customers. Dr. Gisselquist has an M.S. in Computer Engineering and an Ph.D. in Electrical Engineering from the U.S. Air Force Institute of Technology. His current work has been focused on the ZipCPU, and the environment, toolsuite, and peripherals necessary to support both it and any customer applications.

OpenPiton: A Full-Stack Open Source Manycore

OpenPiton is an open source manycore research platform and the world's first open source, general-purpose, multithreaded, manycore processor. The platform is open source from the applications running on Debian Linux at the top, all the way down to the RTL, ASIC/FPGA synthesis scripts, and ASIC backend scripts. ASPLOS '16 Conference Paper.

This talk will discuss OpenPiton's capabilities, some of the systems we have built on ASIC and FPGA using the platform, and the future direction of making it a baseline platform for manycore research in architecture, compilers, systems, networks, EDA, programming languages, and beyond.

Presenter: Jonathan Balkind

Jonathan Balkind is a PhD Candidate at Princeton University, advised by Professor David Wentzlaff. Besides his time spent working on the OpenPiton platform, his research focuses on developing computer architectures inspired by techniques from the world of functional programming.

A 130nm 32-bit RISC-V microcontroller

A complete implementation and measurements of a 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves.

Presenter: Elkim Roa

A professor at Universidad Industrial de Santander, received a B.S. in Electrical Engineering from Universidad Industrial de Santander, Colombia, M.Sc. in Electrical Engineering from University of Sao Paulo, Brazil, and a Ph.D. from Purdue University. I have worked for Rambus designing high-speed SERDES circuits. Currently working on an out-of-order 64-bit SoC.

Automating Hardware Projects with Jenkins

Jenkins is one of the leading open-source automation servers. It’s a framework, which can be adjusted to a particular area with help of its flexibility and plugin system. Many open-source hardware and embedded projects build their Continuous Integration and Delivery flows with Jenkins, because there is not so many tools in the area.

In the talk I would like to cover common use-cases of Jenkins in hardware projects like integration with EDA tools and hardware peripherals like FPGAs and reporting of build, test and coverage reports. After that I’ll share one of two case studies about integration of Jenkins into hardware projects. If I achieve something presentable with the ongoing project by the conference, one of the case studies will be about FuseSoC integration with Jenkins.

Presenter: Oleg Nenashev

Oleg is a member of the core team in the Jenkins open-source project. He has 10 years of experience in hardware and embedded areas (R&D and automation) at companies like Intel, Sitronics and Synopsys. He also has a PhD degree in Hardware Engineering from St. Petersburg Polytechnic University. His R&D activities were related to embedded processor core and IP design; research areas – automated hardware reengineering, branch prediction and SoC architectures. Oleg’s research project at the university was based on OpenRISC. On the automation front he was leading large-scale automation infrastructure projects, which were hosting dozens of HW and SW products. In open-source In the Jenkins project Oleg participates in the core and plugin development, organizes community events like Google Summer of Code and Jenkins meetups.

LimeSDR Demonstration

LimeSDR is an affordable, wideband, 2x2 MIMO software-defined radio (SDR) peripheral that features a Lime Microsystems field-programmable RF (FPRF) transceiver, Altera Cyclone IV FPGA with ~40K logic elements, plus a Cypress USB 3.0 controller. It is open source hardware, with the PCB design database, FPGA RTL and Cypress FX3 firmware all provided under liberal licensing, together with an accompanying host driver.

The LimeSDR board is also very close in architecture to another Myriad-RF design, the STREAM FPGA development platform, for which an OpenRISC SoC design exists with I/Q streaming interface support. The current LimeSDR FPGA platform provides support for features such as digital up/down conversion and sample timestamps (required for e.g. timing critical cellular systems). However, there is also the potential for implementing many other capabilities in the FPGA, in order to offload the host processor, enable support for new applications and perhaps even enable standalone use.

It is proposed to host a tabletop demonstration of the LimeSDR during breaks at ORCONF.

Presenter: Andrew Back

LimeSDR is a project developed via the Myriad-RF initiative, for which I am the community manager.

Open SoC Debug: Bringing up a flexible, scalable debugging framework

System-on-Chip are more and more complex and finding functional errors (bugs) or performance bottlenecks can be very time-consuming and frustrating. The well-known methodology of gdb-like run-control debugging is limited when it comes to observation of a running SoC to discover concurrency problems and other effects. Trace debugging has gained importance, where the processor and other SoC components emit trace events during execution.

Even though debug infrastructure is an essential part of any SoC design, most people consider creating it more of a necessary chore than an exciting endeavor and especially for open source projects a good debug infrastructure is often not considered important enough.

We have started Open SoC Debug as a flexible frmework of hardware building blocks and the software infrastructure to ease the deployment of modern, scalable debug in your SoC.

This talks gives an overview of our goals and the state of the project. I will demonstrate examples of the integration in the lowRISC project and the OpTiMSoC project.

Presenter: Stefan Wallentowitz

Stefan has started the Open Tiled Manycore System-on-Chip (OpTiMSoC) during his PhD project and has been active in open source silicon community since then.

GAP8: A PULP/RISC-V based SoC IOT processor

Greenwaves is a 1.5 years old fabless semidconductor startup based in France. It is willing to offer the first IOT processor. Their first product, GAP8, strongly leverage on PULP and RISC-V open source initiative. GAP8 combined the characteristics of an ultra low power micro controller with uW standby power with the multi GigaOp/s processing capabilities thanks to a cluster of 8 processors. This unique combination makes GAP8 usable for software defined radio applications in order to enable a large range of connectivity scenari but also for advanced processing of data coming from sensors (image, sound and vibration) allowing content understanding.

In this talk we will present the GAP8 SoC and will focus on how the SoC performs on real life applications, in particular how the performances are scaling as a function of the number of cores involved.

Presenter: Eric Flamand

Eric Flamand got his PhD in Computer Science from INPG, France, in 1982. For the first part of his career he worked as a researcher with CNET and CNRS in France, working on architectural automatic synthesis, design and architecture, compiler infrastructure for higly constrained heterogeneous small parallel processors. He then held different technical management positions in the semiconductor industry, first with Motorola where he was involved in the architecture definition and tooling of the StarCore DSP. Then with ST microelectronics first being in charge of all the software development of the Nomadik Application Processor and then in charge of the P2012 corporate initiative aiming at the development of a many core device.

He is now co-founder and CTO of Greenwaves Technologies a French-based startup developing an IOT processor derived from PULP. He is also acting as a part time consultant for ETH-Z and represents ETH-Z at the RISC-V foundation.

Open Source Heterogeneous AMP Virtual Platforms built using the SystemC and TLM standards

As industrial demand grows for modelling, simulation and exploration tools, especially during SoC design and software development, there is a need for models that work with industrial standards and the other tools in the design space.

This presentation will focus on building virtual platforms using open source models using the SystemC and TLM standards; specifically a range of CPU models based on QEMU called QBox. The presentation will cover an open source heterogeneous virtual platform which uses multiple host threads and achieves significant performance. We will examine how QBox works and the limitations they have with respect to TLM and SystemC.

Presenter: Guillaume Delbergue

Guillaume Delbergue is a Ph.D student at GreenSocs and IMS-Bordeaux (University of Bordeaux). His thesis focuses on the standardization of interfaces in SystemC.

VDT - Free Software Environment for FPGA Development

Proprietary FPGA development tool chains still dominate in the world of electronic design especially for the high-end products. While vendors have artificial advantage over the users of their silicon who do not have access to the internals of the devices (other than by reverse engineering) it is not applicable to the higher level of the design tools and their interaction.

VDT isolates proprietary tools operations to specific tasks keeping the developer in the full control of the design using familiar Eclipse IDE. It provides an extra interface level between the plugin and the tools – an XML-based Tool Specification Language (TSL) that makes it possible to fully integrate various implementation and simulation utilities by the end user. TSL keeps the tool customization code at a vendor-agnostic level and so prevents any lock-in.

Presenter: Andrey N. Filippov

Andrey Filippov is a founder of Elphel – a company that provided users with the Free Software/Open Hardware high performance cameras since 2001, all products released under GNU GPL and CERN OHL licenses. Elphel cameras were used by many scientific projects and in Google Books and Street View programs.

MyStorm: An Open Source FPGA board for the IceStorm tool chain

The world of free and open source silicon chip design is going through a period of great innovation, driven by the development of easy to use open source tools, low cost FPGAs and low cost low volume manufacturing.

The MyStorm board was developed by Alan Wood and Ken Boak. It combines a Lattice Ice40 HX4K FPGA with an ARM Cortex M3 on a board with 13 PMOD ports and a Raspberry Pi header that will retail for $30. The board is designed from day one to be used with Clifford Wolf's IceStorm FOSS EDA tool chain.

The first batch of boards from China arrived in the UK on 1 September and were up and running at the OSHCamp workshop on 4 September.

In this talk we'll present the story of how Alan and Ken went from a talk in the pub after a BCS/OSHUG meeting to a full board production run in 100 days. We'll outline the plans for future development and of course demonstrate the board in action.

Presenters: Ken Boak, Alan Wood, Jeremy Bennett

Ken Boak got his first soldering iron on his 6th birthday, and was introduced to electronics by his father, by constructing crystal sets together. He studied Electronic Engineering at the University of North Wales, Bangor, and then went on to work for BBC Research Department on the then, fledgling HDTV systems. Since leaving the BBC in 1994, Ken has held 10 permanent positions, plus several contract jobs across a wide range of hardware disciplines. Ken still enjoys tinkering with the latest hardware and has interests in FPGAs, soft core processors and educational hardware.

Alan Wood has been working with parallel distributed programming for several decades. His recent work includes smart grids, 3D printers, robotics, automation and biotec diagnostics. His current research is focused on machine learning for embedded applications using Motes on FPGA and emerging ASICs. He is a long term advocate and moderator (aka Folknology) for xCORE and other opensource communities, as well as a founder of Surrey and Hampshire Makerspace.

Jeremy Bennett is Chief Executive of Embecosm, which develops free and open source compiler tool chains for companies around the world. He is trying to get the AAP design up and running on IceStorm.

The state of OpenRISC: Documentation, Toolchains and Linux

Other than the OpenRISC CPUs and surrounding hardware cores we have the soft aspects of the project. I would like to give an overview of what I have been working on over the past year and what is in store for the future of documentation, the toolchain and Linux ecosystem.

I started off interested in the Linux port. We will go over the changes I have made as well as progress on getting changes upstream.

We will go over the state of to the toolchain, including getting the last changes out of the `or1k-src` project, specifically GDB and binutils. This will also be followed up with what is needed to get changes upstreamed.

Wrapping it up, the documentation for the project is split between a few different places including the opencores media wiki. Often we in #openrisc get people who have been using old versions of the toolchain pointed to by old docs. I would like to present my thoughts on what we can do going forward.

Presenter: Stafford Horne

As a typical computer hobbyist my background starts with a BS in Computer Engineering from San Jose State University which is where I learned RTL design and Verilog (more than 10 years ago), although I have no problem with VHDL either.

I kept an interest in hardware but have a job in software. In the past few years I have started to really get back into hardware design, both analog and digital. I designed a very simple SDRAM controller in Verilog for the de0 nano. I hooked up a self designed preamp circuit, dac chip and amp to the de0 nano and built a small digital recorder (all hardware, all on github, and demo on youtube) I then looked into running linux on the de0 nano and found OpenRISC.

RC/MC - Pipeline Integrated Message Passing

Although recent manycore architectures (e.g. Intel SCC, Kalray MPPA) offer hardware support for message passing, it is still costly: the sender writes the message in its local memory, a DMA transfer is used to copy the message to the receiver's local memory and an additional signalling mechanism is used to notify the receiver.

The Reduced Complexity Many Core (RC/MC) architecture uses a different approach: by resticting the message length to the size of a data word, special instructions can be used to send and receive messages directly from the processor pipeline. The interconnect is controlled directly, no clumsy memory accesses are involved. This leads to an architecture, where a minimalistic network-on-chip connects small RISC-V cores with private isolated memories.

Presenter: Jörg Mische

Jörg Mische is postdoc researcher at the University of Augsburg (Germany). His group investigates the parallel real-time capabilities of the RC/MC architecture.

Improving mor1kx Cappuccino performance: using PCU and branch predictors as a case study

In this presentation we introduce a way to examine the performance a new implementation of the OpenRISC 1000 arch specification, mor1kx, the fastest version of its pipeline called 'Cappuccino'.

To understand what happens inside the Cappuccino, we implemented Performance Counter Unit (PCU) according to the OpenRISC design specification, and we suggest extensions to this specification in order to make performance evaluation process more effective.

The branch predictor module is chosen as a case study to test our approach in performance tuning for 'Cappuccino', testing included implementation of several branch predictors in verilog and additional evaluation in the software framework with different branch predictors running traces of real programs obtained from mor1kx Cappuccino: static, saturation counter, gshare, bimodal, perceptron, etc.

We overview problems and difficulties of the existing infrastructure we encountered during our efforts and suggest ways to make the whole process easier for further researches.

Presenters: Alexey Baturo, Andrew Voroshilov

Engineers who are interested in performance improvement of mor1kx project.

Application development co-design for FPGA-accelerated data center HPC servers

Scaling the number of cores cannot meet any longer HPC servers performance requirements within power and general costs constraints. As a result, there is a growing interest in the use of FPGAs as an HPC platform with dramatically reduce energy requirements.

Two essential ingredients of this strategy, which is pursued by all key FPGA providers, are the availability of both state-of-the-art compilation, performance analysis and debugging tools, and of a variety of libraries with off-the-shelp pre-optimized commonly used algorithms.

We report the results of one such effort, supported by Xilinx, that is aimed at implementing HPC algorithms, modeled in OpenCL, on an FPGA platform via High-Level Synthesis. The OpenCL kernels and the synthesis scripts are made available as open-source in order to seed the development of the eco-system.

We present preliminary results that demonstrate the development flow as well as the energy efficiency gains.

Presenter: Mihai Lazarescu

Mihai Lazarescu received his M.Sc. in Electrical Engineering from University Politehnica of Bucharest (Romania) and his Ph.D. in Electronics and Communication from Politecnico di Torino (Italy). He co-authored several books on numerical analysis, IoT and HW/SW co-design, more than 40 scientific articles, and thee patents and applications in USA and Italy.

He designed ASICs for research and industrial applications, a platform for embedded software performance estimation, compilation tools for reconfigurable processors, the hardware, firmware and software of a full-custom WSN platform as principal architect, drivers and applications for real-time embedded Linux, and acted as advisor for technology transfer to SMEs. He founded and co-founded several startups and served as associated editor, technical program chair, committee member and scientific articles reviewer for international conferences and journals. His interests include distributed environmental and human activity monitoring, high-level synthesis of hardware and software for embedded systems, and legacy software parallelization.

A Cost-effective System for Neuroscientific Research

In recent times, the fields of EEG application have widened from those typical of the clinical setting to include Brain-Computer Interfaces (BCI) and also consumer-oriented applications ranging from home care to neurofeedback and gaming controllers. There is therefore a demand for high-quality acquisition systems whose montage is fast and does not require trained personnel.

For these reasons we developed an open-source cost-effective, quick-setup EEG acquisition system which can be plugged on the top of an Arduino board. Together with the board we developed a Java-based graphical user interface (GUI) that can be used to acquire, filter, visualize and store EEG signals in real-time and a set of libraries which allows to interface the device with BCI tools.

Presenter: Matteo Chiesi

Matteo Chiesi received the MS degree in electrical engineering from the University of Modena and Reggio Emilia, Modena, Italy, in 2009 and the PhD degree in Information Technology at the Advanced Research Center on Electronic Systems (ARCES), part of the University of Bologna, Italy in 2014. In 2013, he was a visiting student at the Department of Computing, Imperial College London.

Kactus2: Open Source IP-XACT tool update

Kactus2 is the most widely used graphical open source IP-XACT tool for packaging and integrating IP-blocks for System-on-Chip designs. It features the complete IP-XACT design flow, e.g. Verilog/VHDL file import, component, design and configuration editors and code generators.

In the last year the tool has undergone some major changes and improvements. We will introduce the latest updates, new features and discuss the future plans for Kactus2.

Presenter: Esko Pekkarinen

Esko Pekkarinen received the MSc degree in 2013 from Tampere University of Technology (TUT) in Finland. His MSc topic was wireless sensor network simulation with OMNeT++. Since then he joined the Kactus2 open source IP-XACT tool project and acts now as the chief SW architect of the project. He is currently a researcher and PhD student at TUT.

Sponsors

ORCONF and FOSSi are looking for sponsors help to cover the costs of this year's event.
Please get in touch if you'd like to support us this year.

You can also support us with small donations via Paypal:

Questions? Contact the organisers or ask in #fossi on irc.freenode.net