An open source digital design conference

We're pleased to announce that ORCONF 2015 will be held between October 9 to October 11 at CERN, the European Organization for Nuclear Research, in Geneva, Switzerland.

ORCONF is an open source digital design and embedded systems conference, covering areas of electronics from the transistor level up to Linux user space and beyond. Expect presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name a few.

Begun as the annual OpenRISC developers and users conference, it has become a broad open source digital design-oriented event. This year ORCONF is run as a Free and Open Source Silicon (FOSSi) event, further broadening its remit, and as such will include a lowRISC workshop on the Friday.

Venue

The conference will take place at CERN in Geneva, Switzerland.

A map of the CERN Meyrin campus with the buildings for ORCONF is available here as PNG and here as PDF.

Arrival guide

The main way in and out of CERN from/to the city is tram line 18, with an end-of-line stop facing building 33.

Geneva's public transport portal is http://www.tpg.ch/

The number for a taxi is +41 (0)22/320-22-02

Registration and access to CERN

An ORCONF registration desk is organized on Friday 9th October from 11:30 to 12:15 in building 33 , CERN main reception (in front of the tramway stop). Your access badges (mandatory for the access to CERN) will be delivered during this registration. If you arrive outside these times, your badges will be kept by CERN main reception in building 33.

Friday venue

The venue for Friday's sessions is 6-2-024 (BE Auditorium). That's building 6, floor 2, room 24. Map link.

As people will be arriving at around lunch time on Friday, we'd suggest having lunch at Restaurant 1 prior to the beginning of proceedings at 1PM.

Saturday, Sunday venue

The venue for Saturday and Sunday's sessions is the Filtration Plant, room 222-R-001. Map link.

Search buildings on CERN's directory (http://directory.web.cern.ch/directory/) by selecting "CERN map" in the drop-down menu and typing in the building number.

Laptop registration

To have access to the CERN network with your portable computer, please fill out the form in the following link: https://network.cern.ch/sc/fcgi/sc.fcgi?Action=TrueVisitorRegistration

When prompted, specify your contact at CERN is SERRANO, Javier, email: Javier.serrano@cern.ch

We strongly recommend you apply for access prior to arriving at CERN as your access request needs first to be approved.

Lunch and coffee breaks

The sponsored lunches on Saturday and Sunday will take place in Restaurant 1 NOVAE (building 501) which is a few minutes walk from the conference rooms.

You will be provided with a coupon of 10 CHF in value which you can use in the restaurant. Note that the difference is not refundable.

The sponsored coffee breaks at 3PM on Friday and Saturday will be located at the conference rooms.

Restaurant 1 will be open from 7AM until 5:30PM each day and will be available for drinks and snacks during other breaks.

Dinner on Saturday evening

For those of you that registered, the dinner at is at 8PM. We will provide instructions on getting there on Saturday.

Practicalities

Money

The official currency in Switzerland is the Swiss Franc (CHF). Exchange facilities are available at the airport and at the branches of banks. Please note that the UBS bank is located in the CERN site.

Visa

Given that the Organization is located on the border between France and Switzerland, we strongly recommend that you contact the relevant consulates for information on the entry conditions applicable to you in these two countries.

Power adapters

Switzerland has its own power socket standard, type J, which is similar to the usual continental Europe socket except that it has the addition of a grounding pin. The Conference rooms will have Swiss electrical outlets but standard European type C plugs will be usable.

2015 presentations and bios

PULP: OpenRISC-based ultra-low power parallel platform

PULP is an open-source parallel, low-power architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability. The PULP platform targets a number of high-growth application areas such as internet of Things, E-health, wearable Human-Computer interfaces. The PULP project currently involves several universities and research centers in Europe including University of Bologna, Swiss Federal Institute of Technology Zurich (ETHZ), Politecnico di Milano, Swiss Federal Institute of Technology in Lausanne (EPFL), and Laboratory for Electronics and Information Technolog­y of Atomic Energy and Alternative Energies Commission (CEA-LETI). This talk will describe the aims of the PULP project, and summarize its current status and plans for future evolutions of the project.

Presenter: Francesco Conti

Francesco Conti obtained his MSc degree in Electronic Engineering at the University of Bologna in December 2012 and, since January 2013, he is pursuing a PhD in the Department of Electrical, Electronic and Information Engineering of the University of Bologna, in the group led by Prof. Luca Benini. From January to April 2015, he has also been a visiting PhD Student in the Robust Systems Group at Stanford University, led by Prof. Subhashish Mitra.

AAP: An Altruistic Processor

An Altruistic Processor (AAP) is a free and open source processor ISA, intended as reference architecture to improve software tool chain support for small, deeply embedded Harvard architectures. These are still in very widespread use (for example the Atmel AVR architecture), but compiler tool chains often suffer from assuming all targets are 32- or 64-bit Von Neumann RISC architectures with many registers (such as ARM).

AAP is a 16-bit Harvard architecture, with a 24-bit word addressed code space. It can be configured with as few as four 16-bit registers and has an extensible instruction set offering 16-bit, 32-bit and longer instructions. It thus provides a robust test of the generality of modern compiler tool chains.

Embecosm has implemented a LLVM tool chain and instruction set simulator for AAP, and is in the process of creating FPGA implementations in Verilog for the DE0-Nano.

In this talk, we will explain in detail the feature and philosophy of AAP as well as some software features we aim to improve through this project. We will present the implementation of both the ISS and the FPGA designs, one of which is a simple student implementation, and the other a superscalar pipelined implementation.

Presenters: Simon Cook, Ed Jones, Jeremy Bennett, Dan Gorringe

Simon Cook has a background in low-power processors, with a particular focus on the energy constraints of code running in embedded environments. He also provides support for Embecosm's work on low level binutils for both GNU and LLVM toolchains. Simon is a graduate of the University of Bristol, where he achieved joint First Class Honours in Computer Science and Electronics.

Ed Jones has a background in parsing techniques and supports Embecosm’s work on runtime libraries, LLVM toolchains and testing. Ed is a graduate of the University of Kent where he achieved first class honours in Computer Science.

Embecosm was founded by Dr Jeremy Bennett, an expert on hardware modeling and embedded software development. Previously Dr Bennett was Vice President of ARC International plc, following their acquisition of Tenison Design where he had been CEO and CTO. Dr Bennett is author of the popular textbook, “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003) and holds an MA and PhD in Computer Science from Cambridge University.

Dan Gorringe is a student at Brockenhurst College, UK, studying for Maths and Physics 'A' Levels. As a 15-year old intern at Embecosm he wrote the application note "Silicon Chip Design for Teenagers", an introduction to FPGA design for school students.

Xeons + FPGA and enabling Open Source third party IP

Gaurav Kaul discusses the use of accelerators on Intel platforms to deliver better performance efficiency for targeted workloads. He addresses the use of FPGAs as a programmable accelerator and the recent trend of leading cloud service providers and telco service providers investigating the use of FPGA accelerators for differentiation and customization.

The discussion also covers Intel’s recent announcement of the Xeon+FPGA integrated product concept and presents our plans to bring this concept to market. We will also discuss how this will enable 3rd party IP vendors to have a wider reach by putting their IP on Xeon+FPGA platform.

Presenter: Gaurav Kaul, Solutions Architect, Intel Corporation

Setup and hold - The past and future of OpenRISC

A rundown of the OpenRISC project's history and current state

Presenter: Olof Kindgren

Open Source HDL Synthesis and Verification with Yosys

Yosys (Yosys Open Synthesis Suite) is an open source project aiming at creating a fully-featured HDL synthesis tool, and more. Lately a lot of features related to formal verification have been added to Yosys.

Project IceStorm aims at documenting the bit-stream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bit-stream files, including a tool that converts iCE40 bit-stream files into Verilog.

Arachne-PNR is a place&route tool based on the databases provided by Project IceStorm. It converts BLIF files into an ASCII file format that can be turned into a bit-stream by IceStorm tools.

This three projects together implement a complete open source tool-chain for iCE40 FPGAs. It is available now and it is feature complete (with the exception of timing analysis, which is work in progress).

This presentation covers the open source Yosys-IceStorm-Arachne iCE40 flow as well as some other synthesis and verification applications based on Yosys.

Presenter: Clifford Wolf

Clifford Wolf is the author of Yosys and Project IceStorm, among other open source projects. He is probably best known for being the original author of OpenSCAD. His open source lib(X)SVF library somehow made it into the field bus system used in CERN's LHC (CernFIP).

Interpretation of LGPL and GPL for HDL designs

TBD

Presenters: Javier Serrano, David Mazur, Charlyne Allison Rabe

Small footprint RISC-V core in Verilog

A lightning talk on the development of a small footprint RISC-V core in Verilog HDL targeted at low-end usecases.

Presenter: Tomasz Wlostowski

Axiom 4K open filmmaking camera - a success story of collaboration around open source

The successes of the open source and open hardware movements have been huge in many areas, but less so in explaining why a commercial company would want to get involved in it. I will describe why Antmicro decided to participate in an open-source, open-hardware 4K camera project and why everyone in their right mind would have decided the same if they were us.

The Axiom Gamma project is a good case study of how thanks to open source you can grow your business while doing the 'right thing' (TM). I will briefly describe some history behind the project - how did three companies, one university and one non-profit come to work together - and factors that were important for its success so far.

Presenter: Michael Gielda

Cocotb

Cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.

Using Python for functional verification makes it possible to rapidly create complex testbenches with minimal overhead. The ability to glue together existing software or external systems is very powerful, allowing us to integrate software much earlier in the development process and utilise block level simulation as a software development target.

This introductory talk will provide a brief overview of the project before delving into some real-world examples that might be difficult to achieve in other simulation environments, such as cosimulation of kernel driver software and RTL.

Presenter: Chris Higgs

Shakti RISC-V processors

SHAKTI is a family of processors based on the RISC-V ISA and targets all the major segments of the processor spectrum, ranging from IoT class controllers to server/HPC class server parts. One of the class in series of processors, the I-Class is aimed at mobile and desktop environments. The design is highly parametrized to facilitate quick design space exploration. It is an Out-of-Order core, with pipeline depth of 8 stages, based on merged register file approach.

Another class of series of processors, the F-Class, employs ECC to tolerate errors in registers and memories and uses space and time redundancy based techniques to tolerate errors in ALU.

In this talk, we will present the design and performance characteristics of I-Class processor and fault tolerant techniques employed in ALU of the F-Class.

Presenter: Rahul Bodduna, RISE Group, IIT Madras

Reduced Complexity ManyCore (RC/MC)

The RC/MC architecture consists of a large number of small RISC-V processor cores that are connected by the real-time capable PaterNoster Network-on-Chip. In contrast to conventional multicores there is no shared memory or cache hierarchy. Instead, each core has a small private memory and communicates with the other cores via explicit fine grained messages.

Small cores provide a high performance/Watt ratio and a good timing predictability. Therefore we investigate, if the RC/MC architecture can provide the same performance as conventional shared memory multicores with lower energy consumption and better real-time capabilities.

Presenter: Jörg Mische, researcher at the University of Augsburg.

OPA: Out-of-Order Superscalar Soft CPU

OPA is an out-of-order superscalar processor designed for FPGAs. Compared to a traditional ASIC, an FPGA does not have ready access to multiported memory, content-addressable memory, or fast combinatoric circuitry. On the other hand, memory is much faster compared to core clock rate. The cost of a cache miss to DDR on a 4GHz ASIC is more than an order of magnitude more serious than a cache miss to DDR from an FPGA-based design.

The primary challenge in the design of OPA has been finding circuits which are simple enough to run at a reasonable clock rate on an FPGA. Of particular note is the wakeup-select circuit which schedules instructions for execution once their dependants are available. OPA manages this using novel shift and mux circuit with one ready bit and two muxes per pending instruction. While a traditional out-of-order design uses a separate reorder buffer and instruction scheduler, the low cache miss penalty makes it possible for OPA to use a simple unified circuit for both.

As FPGAs come in many different sizes, so too must OPA. At synthesis time, one can select the number of execution units, the scheduler window size, and the supported instruction set (currently only LM32 or RV32M). On a low-end Cyclone V, a 4-decode 3-issue processor which schedules up 28-instructions at once can run at 125MHz in 10k ALMs. The smallest configuration costs 4k, but there is no upper limit on the issue width and cost. However, OPA does not yet include a TLB or ITTAGE predictor, so these costs will increase.

Presenter: Wesley W. Terpstra

Wesley currently works on FPGA-based embedded systems at the GSI Helmholtz Centre, primarily Wishbone-based System-on-Chip designs. He received his Dr.-ing. in Computer Science from the Technische Universitaet Darmstadt in 2015 and his B.Sc. in Mathematics and Computer Science from the University of British Columbia in 2003.

A fast RISC-V emulator in Javascript - How hard can it be?

Running a complete Linux system directly in the Web browser? Why? Just because it's possible or does it have some real world applications? In this talk we will address this question for the emulator jor1k. jor1k for the OpenRISC architecture started as as a pure fun Open Source project with less than 1500 lines of code but has now become the fastest and most flexible Linux emulator for the Web.

This year jor1k was part of the Google's GSoC program in order to implement the RISC-V CPU. Hence, this talk will not only address the question above, but will especially focus on the inner working of jor1k, the new RISC-V implementation and several subsystems like network support and the unique filesystem.

Presenter: Sebastian Macke

Sebastian Macke did his Ph.D. in Physics in Stuttgart at the Max-Planck Institute for Metals Research and is currently Postdoctoral fellow at the Max Planck - UBC centre for Quantum Materials, where he works on the physics of strongly correlated electron systems. In his "free" time Sebastian Macke is engaged in several open source projects and is known for his OpenRISC emulator jor1k.

Kactus2: Open Source IP-XACT tool

Kactus2 is the most widely used graphical open source IP-XACT tool aimed at packetizing and integrating IP-blocks for System-on-Chip designs. Kactus2 has import wizards for legacy Verilog and VHDL code, easy to use editors for IP-XACT components and designs, and code generators for HW synthesis flow and HW dependent SW development. The Kactus2 project was launched in 2010. Since then it has grown to a full-fledged IP-XACT design tool. We will introduce the project and present the features and future of Kactus2. We propose Kactus2 as the integration tool framework for open System-on-Chip projects.

Presenters: Timo D. Hämäläinen and Esko Pekkarinen

Timo D. Hämäläinen received the MSc degree in 1993 and PhD degree in 1997 from Tampere University of Technology (TUT) in Finland in electronics and computer engineering. He has been a professor at TUT since 2001. He is (co)author of over 70 journal and 220 conference papers and holds several patents. His past research activities include neural network implementations, on-chip interconnections and wireless sensor networks. The ongoing research includes design methods and tools for multiprocessor System-on-Chip development and HEVC video encoder implementations on embedded and high-performance platforms.

Esko Pekkarinen received the MSc degree in 2013 from Tampere University of Technology (TUT) in Finland. His MSc topic was wireless sensor network simulation with OMNeT++. Since then he joined the Kactus2 open source IP-XACT tool project and acts now as the chief SW architect of the project. He is currently a researcher and PhD student at TUT.

An update on the lowRISC open source System-on-Chip

The lack of a secure, flexible, high performance, and silicon-proven open source base for SoC designs holds back innovation and rate-of-progress in the semiconductor industry. The not-for-profit lowRISC project aims to rectify this, building on the open RISC-V instruction set architecture and exploring ideas on improving security via tagged memory and increasing flexibility through the addition of RISC-V 'Minion' cores to implement soft peripherals. Put simply, lowRISC aims to become the Linux of the hardware world. This talk will give an update on our efforts and our path to first silicon and low cost development boards (Raspberry Pi for grownups!), including how the open source community at large can get involved.

While the potential advantages of open-source software have been clearly demonstrated, the benefits remain untapped in the semiconductor industry. We believe there are significant gains in promoting the open development of hardware without imposing restrictions on its modification or use. Today, it would be almost inconceivable to start work on a large software project without building on an existing open-source base. lowRISC and the wider open-source hardware movement will have succeeded when the same can be said of new projects in the semiconductor industry.

Presenter: Alex Bradbury

Alex Bradbury is a compiler hacker and researcher at the University of Cambridge Computer Laboratory. He is a co-founder of the lowRISC project and has been an active contributor to the Raspberry Pi project since the availability of the first alpha hardware. He also curates the popular 'LLVM Weekly' development summary.

TCP/IP Offload to Minion Cores using Rump Kernel

Rump kernels are a framework for running the free, portable, and production-quality NetBSD drivers and subsystems on various platforms. As part of this year's lowRISC Summer of Code, rump kernels were ported to bare-metal RISC-V. The purpose of the port was to use rump kernels on the so-called minion cores, lowRISC's peripheral I/O processors. As an example application, a prototype for offloading TCP/IP to the rump kernel is presented, but the concept and implementation are reusable and fit other applications just as well.

This talk will present the work done in this LSoC project, but also give a general introduction to rump kernels and how they can be used in other similar scenarios.

Presenter: Sebastian Wicki

Sebastian Wicki is a Master's student at ETH Zürich. This Summer of Code project was his first, but surely not last contact with rump kernels and the RISC-V ecosystem.

HardCaml

HardCaml is a structural hardware design DSL embedded in Ocaml. The library can be used for front end design tasks up to the synthesis stage where a VHDL or Verilog netlist is generated. Libraries for fast simulation using LLVM, waveform viewing and co-simulation with Icarus Verilog are provided.

HardCaml-RiscV is a simple pipelined RV32I core, targetted towards a FPGA implementation and built with HardCaml. Future plans include various configurable features.

HardCaml-ZINC builds on HardCaml-RiscV to provide an efficient execution environment for running OCaml bytecode programs on FPGAs. Features include a simple scheme to reduce interpreter overhead, acceleration of common operations and addition of cpu state to suit the stack based architecture.

A fun project goal is to get the HardCaml-ZINC design running on an FPGA and to generate the source code that built it so it can bootstrap itself (sort of!).

Presenter: Andrew Ray

Nerabus: Fostering Open Source Silicon

Nerabus is new global startup with the remit to help foster the Open Source Silicon ecosystem, accelerate its growth and bring the innovative power of this ecosystem to bear on the critical issues in both datacenter and embedded of compute cost, latency, power and scale.

Presenters: Rob Taylor

Rob Taylor has been working commercially with Linux and Open Source technologies since the late 90's. He founded two Open Source software development and consultancy houses, Collabora and Codethink. He is now turning his attention to the exciting potential of Open Source silicon and digital design.

Cosmic PI

CosmicPi is an open source project aiming at creating a low cost and fully open source detector for cosmic rays. The project aims to create a distributed cosmic ray telescope by networking individual pixels located across the globe. Charged particles created by the collision of cosmic rays with constituents of the atmosphere deposit energy in a low cost plastic scintillator. The energy is converted into photons by the material, which are then trapped by wavelength shifting optical fibres to bring the light generated to two silicon photomultipliers. Two sensors are located at opposite ends of the scintillator in order to provide coincidence detection of events. An open hardware front end, including amplifier, pulse shaper and trigger functionality is currently under development. Control of the device and data acquisition is handled by an Arduino DUE, which provides JSON formatted output to a Raspberry Pi for analysis and upload to the detector network. The CosmicPi architecture includes a comprehensive array of environmental sensors including barometer, accelerometer, magnetometer, relative humidity and GPS to allow citizens and scientists alike to study how cosmic rays interact with the world around us.

This presentation will focus on the detector architecture and the hardware challenges overcome so far.

Presenter: James Devine

James Devine is an Electrical Engineer at CERN. He has experience working on all aspects of the design and installation of large scale electrical infrastructure projects and mission critical facilities, including UPS and emergency diesel generators. In his spare time he likes to make electronics and has experience in launching balloons to the edge of space, building robotic arms based on Arduino and prototyping software in Processing and Python.

Z-scale: Tiny 32-bit RISC-V Systems

This talk introduces Z-scale, family of tiny 32-bit RISC-V cores, and gives an update on its implementation status. We also present recent updates on the Rocket Chip Generator, and how the Z-scale system fits within the generator framework. We also discuss future directions of the Rocket Chip Generator, including memory-mapped I/O support and JTAG debugging.

Presenter: Yunsup Lee

Yunsup Lee is a PhD candidate in Computer Science at UC Berkeley and a member of the Computer Architecture group in the ASPIRE lab. He is working on RISC-V, a free and open ISA, and future data-parallel architectures (checkout http://hwacha.org) to make computer systems more energy-efficient. He has recently co-founded SiFive, Inc. to provide commercial support around the RISC-V ecosystem.

RISC-V Update

This talk will present an update on the RISC-V project from UC Berkeley. Recent ISA developments include advanced draft proposals of the privileged and compressed specifications, and preliminary design of the vector extension. Recent RTL implementation progress includes the Z-scale microcontroller generator (to be presented separately) and the BOOM superscalar out-of-order processor generator. The talk will also describe the non-profit RISC-V Foundation, which has now been incorporated.

Presenter: Krste Asanović

Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007 where he is Director of the Berkeley ASPIRE lab, tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-V ISA project, is Chairman of the RISC-V Foundation, and has recently co-founded SiFive Inc. to support commercial use of RISC-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

ORXSys - OpenRISC based eXtendible System

ORXSys means OpenRISC based on eXtendible System. This project aims to provide a platform for fast application development based on FPGA boards. This lightning talk will introduce its status and the future plan

Presenter: Alex Guo

Alex Guo, Embedded System Design Manager, Credo Semiconductor.

Previous editions:2014, 2013, 2012

Travel and accommodation

CERN hotel

There is limited availability of accommodation on site for the nights of the 9th and 10th of October.

Please note that the CERN hotel's booking policy prohibits them from accepting bookings for people from private companies who are attending the conference.

A booking can be made on their site. You will have to specify that you're visiting CERN for ORCONF and that the guarantor at CERN is Javier Serrano (Javier.Serrano@cern.ch).

Hotels in the local area

CERN have a list of hotels in the local area.

People can consult the list of hotels and then send a mail to the Housing service of CERN, cern.hostel@cern.ch requesting to make a pre-booking.

Please note that the Housing service will be only the intermediate in order to have the special rates. Participants will be in copy of the pre-booking and they will have to finalise the reservation by themselves (usually via payment) directly with the hotel.

Sponsors

Questions? Contact the organisers or ask in #openrisc on irc.freenode.net